1. Field of the Disclosure
Embodiments of the present invention relate to a complementary junction field effect transistor (c-JFET) and its metal gate-last fabrication method of a c-JFET device.
2. Description of the Related Art
Currently, with the continuous shrink of the size of transistors, the High-k insulating layer plus metal gate (HKMG) technique has been almost an indispensable selection for fabricating small size transistors. With regard to the processes of fabricating transistors with HKMG structures, two fabrication processes are available, that is, a gate-first process and a gate-last process. It is generally considered that the difficulty of forming HKMG structures through the gate-first process may arise in the control of the threshold voltage of PMOS transistors. In order to lower the threshold voltage of PMOS transistors, the structures and designs of the semiconductor device should be greatly modified in the gate-first process, which may disadvantageously increase process complexity and fabrication costs. Thus, the inventor of this invention deems that the gate-last process is more preferable for PMOS transistors.
Presently, complementary junction field effect transistors (c-JFET) have been widely used in many applications. However, all fabrication methods of c-JFET are gate-first methods. There isn't any gate-last fabrication method for c-JFET introduced and applied in the prior art, and no such a fabrication process is introduced in related literatures as well. The inventor has found that fabricating c-JFET through metal gate last fabrication methods can produce highly favourable effects.